What Does onTAP Test?
As boundary scan technology grows in popularity, more JTAG compliant devices (1149.1 and 1149.6) are now being included in board design, along with more JTAG chains that often require simultaneous testing.
The great advantage to using onTAP, is that there are no restrictions on the number of devices in a chain that it can test. Using just one onTAP TAP CONNECT JTAG Cable, onTAP can test two chains simultaneously. Testing more than two chains in parallel can be achieved in one of two ways:
- Multiple TAP CONNECT JTAG cables may be used to test chains simultaneously.
- Serializing chains can be accomplished using the onTAP GPIO Serializer, a single TAP CONNECT Cable, and merged netlists (a task performed by onTAP).
onTAP will perform several critical tests on your board such as:
- TAP Infrastructure/ID Code Test
- Interconnect Test
- Mid-state/Resistive Shorts
- Incorporating Multi-die devices
- Opens and Shorts Tests
- Pull Up/Pull Down
- I2C Bus Control and Test
- Memory/Flash Test & Programming
- Cluster tests
- 1149.6 – AC Coupled Circuit/Differential Pairs
onTAP requires just three items to begin developing a test:
- BSDL Files for all JTAG compliant devices on the board
- Board Netlist
- An onTAP- TAP CONNECT JTAG Cable
An Overview of Some Tests Performed with onTAP
The first test is the TAP (Test Access Port) test. Since JTAG Boundary Scan is essentially a test instrument built into your board, it is important to check the test instrument before beginning a test. Any infrastructure test through device TAPs (Test Access Ports) accomplishes this and in the case of a fault, alerts where a boundary scan chain is broken.
Once the TAP has been verified, the next test is the Interconnect Test.
A connectivity test, or Interconnect Test, is the foundation of any boundary scan test solution. This test verifies that devices are properly connected to your board with no opens or shorts, especially common with BGAs. onTAP’s automatic test pattern generator (ATPG) generates test patterns to ensure that boards are free of defects including opens, stuck-ats-shorts and mid-state/resistive shorts.
Mid-State / Resistive Shorts – Nasty, Tough to Isolate, Show Stoppers
A major problem that often goes undetected by typical boundary scan connectivity tests are mid-state/resistive shorts. While the typical connectivity tests will locate the short between nets 3 and 4 in the example below, they cannot locate the resistive short which exists between nets 1 and 2. This type of short is a mid-state condition, and is recognized and diagnosed. (See our application note on Interconnect testing for more information.)
Bus Wire – Managing Multiple Outputs on a Net
The onTAP-Specific Interconnect test manages bus wires when multiple outputs are connected to a net. onTAP verifies each pin has the chance to drive the output high and low while all inputs capture values.
Cluster Testing – Accessing, Testing, Programming and Controlling non-JTAG Devices
onTAP uses the high-level DTS test language (see application note and DTS Programming Manual to learn more about this dynamic, C-Like, reusable language) to develop reusable test models for testing connectivity between scan devices and non-scan devices such as DDR2, SRAM, SDRAM, and FLASH. onTAP’s Cluster Test also provides a means to program FLASH memory and configure logic.
For more information regarding onTAP or Boundary Scan, contact Flynn
systems at (603)-598-4444 or visit the website at www.flynn.com.