Chip manufacturers are now producing multichip modules (MCMs) that may include two or more arrays of devices within a single package. These modules can be tested using JTAG test pattern generation of the devices while on a PCB.
To incorporate JTAG testing of MCMs there are several things that are needed: a netlist of the MCM and the BSDL files. Netlists may be available from the module manufacturer or they may be created by the JTAG test software. BSDL files should be available from the manufacturer.
Since MCMs are arrays of JTAG-compliant devices they cannot be thought of as single JTAG devices. To begin the process, the netlist for the MCM must be merged with netlist of the PCB on which it is mounted.
The BSDL files for the MCMs are separate for each part of the array, usually with a <devicename>_A1.bsd, <devicename>_A2.bsd, BSDL file names until all parts of the array are defined.
If your boundary scan application includes multi-chip modules, you will want to make certain that your boundary scan software tool has the capability to effectively test these modules. onTAP includes a tool to merge the array of MCM netlists with that of the PCB into a combined file. If a netlist for the MCM is not available, one can be created for each element of the array combining it with the board netlist by using the onTAP software.
The ability to effectively test multichip modules is just another bonus Flynn Systems’ onTAP Boundary Scan Test and Development Software offers. For boundary scan software you can count on, give Flynn a call at (603) 598-4444!