When large numbers of outputs switch simultaneously, they can cause intermittency with your test due the ground bounce effect. JTAG Test with onTAP lets you control this problem by giving you control over how many outputs switch during a single test scan, as shown below: Understanding ground bounce In manufacturing test environments, it’s not […]
Posts Tagged ‘JTAG Test’
Once a board developer passes along the new board and all related files and procedures to a test developer, the boundary scan test process can begin. We recommend including the TAP Integrity Test at the beginning of your interconnect test because the TAP contains pins associated with the test access controller, e g., the TAP […]
Chip manufacturers are now producing multichip modules (MCMs) that may include two or more arrays of devices within a single package. These modules can be tested using JTAG test pattern generation of the devices while on a PCB. To incorporate JTAG testing of MCMs there are several things that are needed: a netlist of the […]
In our last discussion, we talked about DFT, which plays a significant role in reducing costs in prototyping. There are a wide variety of reasons that prototyping is a significant expense in the development and production processes. A large part of the cost is the increasing complexity of designs, inclusion of more processors and FPGA’s, greatly reduced board real estate, and diminishing test access. With the cost of FPGA’s and processors rising as they too become more powerful, getting small batches of devices is expensive. If one of those devices is fried during prototype testing, the cost to prototype a new design escalates rapidly, especially if the cause of the failure isn’t quickly determined.
As electronics production becomes more complex, and more expensive, board designers and manufacturers require tools that are better suited to handling the complexities of new designs. If this sounds like the same story you’ve heard from JTAG test companies for the past 10 – 15 years, it’s because now, more than ever, Boundary Scan Test Software / JTAG test and programming solutions are the best (read: most economical, accurate, safe, reliable, repeatable, consistent, flexible), choice for the handling of modern electronics.
We are constantly exposed to new situations in boundary scan test and new approaches to using boundary scan to achieve better test fault coverage. One item standing in the way of higher, more accurate fault coverage is common tri-state control cells.
We insure that your boundary scan tests are maximized for the highest possible fault coverage, are completely debugged, and are ready to put in the hands of test engineers on the manufacturing floor, so all they have to do is “press a button.”
We support our tests and we will support your manufacturer by answering questions and bringing them up-to-speed with boundary scan test and onTAP.
Mid-state shorts are a major problem that often goes undetected by typical boundary scan connectivity tests is mid-state/resitive shorts. Flynn Systems recognized this “hole” in boundary scan testing and was the first boundary scan test company to test for mid-state shorts, improving test fault coverage.
The goal is to exploit JTAG testing to achieve maximum fault coverage in addition to Flash programming and configuration tasks,” says Hank Flynn, CEO of Flynn Systems Corp. Like so many new features added to onTAP, Flynn’s introduction of the upgraded ATPG was a direct result of meeting customer needs. “Even if a tool has the capability to provide high fault coverage, when too much user intervention is required, chances are fault coverage goals will never be achieved. It’s clear that increased automation throughout the test prep experience is the key.” Says Flynn.