Engineering has many different branches that students can expand into as they complete their college degrees and begin searching in the field for a position. Within the world of electric engineering is the smaller yet essential area of electronic engineering. This area of study can be found at universities like USC and the University of […]
Posts Tagged ‘JTAG boundary scan test’
Mid-state shorts are a major problem that often goes undetected by typical boundary scan connectivity tests is mid-state/resitive shorts. Flynn Systems recognized this “hole” in boundary scan testing and was the first boundary scan test company to test for mid-state shorts, improving test fault coverage.
Once a board developer passes along the new board and all related files and procedures to a test developer, the boundary scan test process can begin. We recommend including the TAP Integrity Test at the beginning of your interconnect test because the TAP contains pins associated with the test access controller, e g., the TAP […]
We are constantly exposed to new situations in boundary scan test and new approaches to using boundary scan to achieve better test fault coverage. One item standing in the way of higher, more accurate fault coverage is common tri-state control cells.
Ontap_parallel.exe can be used to simultaneously run test suites on multiple PC boards using the onTAP DLL. Parallel board testing must be enabled for the DLL license. Testing is fastest on a multiple processor PC , particularly where one core processor is available for each board. For example if four PC boards are being tested in parallel, then a quad core processor is recommended so that the time to test four boards is about the same as that required to test one board.