In an age where technology is king, electric systems have become part of everyday life. From our smartphones to medical equipment every piece of technology has been able to advance, thanks to rapid changes in how we work with electric systems. Innovation and creation are only able to be implemented in society if they have […]
Posts Tagged ‘jtag boundary scan’
The boundary scan test software provides a way to interconnect between integrated circuits (ICs) on a board without using physical test probes. The scan contains cells within a device that can capture data from pin or core logic signals or force data onto pins. The captured data is moved out and externally compared to other […]
If a chain of devices consisted only of boundary scan (JTAG) compliant devices, there would not be too much testing required. However, boards today contain complex, non-JTAG devices that interact with the boundary scan devices. Testing just the JTAG devices on the board is always an option. However, developing a test that takes into account […]
Once a board developer passes along the new board and all related files and procedures to a test developer, the boundary scan test process can begin. We recommend including the TAP Integrity Test at the beginning of your interconnect test because the TAP contains pins associated with the test access controller, e g., the TAP […]
Chip manufacturers are now producing multichip modules (MCMs) that may include two or more arrays of devices within a single package. These modules can be tested using JTAG test pattern generation of the devices while on a PCB. To incorporate JTAG testing of MCMs there are several things that are needed: a netlist of the […]
One of the most common comments we hear from our customers and business partners sounds something like this: “Well, I’ve heard about boundary scan testing, and have actually used it a bit before. Moving forward, we have a new project we need to use it on, and we have a bone pile I might get to.”
Now that your board has moved from prototyping to manufacturing, things are humming along until…there is a snag in manufacturing. Suddenly an entire run of boards is failing for unknown reasons, and you’re already dangerously close to being behind schedule.
In our last discussion, we talked about DFT, which plays a significant role in reducing costs in prototyping. There are a wide variety of reasons that prototyping is a significant expense in the development and production processes. A large part of the cost is the increasing complexity of designs, inclusion of more processors and FPGA’s, greatly reduced board real estate, and diminishing test access. With the cost of FPGA’s and processors rising as they too become more powerful, getting small batches of devices is expensive. If one of those devices is fried during prototype testing, the cost to prototype a new design escalates rapidly, especially if the cause of the failure isn’t quickly determined.
Why SVF? As boundary scan test was making its way to center stage for testing surface mounted devices, there was no agreed upon protocol to manage the hundreds of thousands of bits of IEEE 1149.1 test pattern information. Instead, many vendors had vendor specific protocols for managing the data. In the early 1990s, Texas Instruments […]