In today’s world, there’s no avoiding technology. Whether you consider yourself “tech savvy” or not, there’s no escaping the continuously changing expectations of society. However, with the increasing demands comes a need for increased security.

The boundary scan test software provides a way to interconnect between integrated circuits (ICs) on a board without using physical test probes. The scan contains cells within a device that can capture data from pin or core logic signals or force data onto pins. The captured data is moved out and externally compared to other […]

Boundary scan testing can help you debug your devices, but what do you do when a bug has you completely stumped?

Today’s consumer is provided a variety of options no matter what the subject matter happens to be.  At Flynn Systems we like to keep things simple by providing the best solution in boundary scan options.  Saving the consumer both time and money by avoiding trial and error software, Flynn’s boundary scan is no nonsense and […]

Chip manufacturers are now producing multichip modules (MCMs) that may include two or more arrays of devices within a single package. These modules can be tested using JTAG test pattern generation of the devices while on a PCB. To incorporate JTAG testing of MCMs there are several things that are needed: a netlist of the […]

Who cares. The owner of the problem is not necessarily always the issue. Blame most often gets thrown around the work place when things don’t work, and a resolution is needed.

One of the most common comments we hear from our customers and business partners sounds something like this: “Well, I’ve heard about boundary scan testing, and have actually used it a bit before. Moving forward, we have a new project we need to use it on, and we have a bone pile I might get to.”

Now that your board has moved from prototyping to manufacturing, things are humming along until…there is a snag in manufacturing. Suddenly an entire run of boards is failing for unknown reasons, and you’re already dangerously close to being behind schedule.

In our last discussion, we talked about DFT, which plays a significant role in reducing costs in prototyping. There are a wide variety of reasons that prototyping is a significant expense in the development and production processes. A large part of the cost is the increasing complexity of designs, inclusion of more processors and FPGA’s, greatly reduced board real estate, and diminishing test access. With the cost of FPGA’s and processors rising as they too become more powerful, getting small batches of devices is expensive. If one of those devices is fried during prototype testing, the cost to prototype a new design escalates rapidly, especially if the cause of the failure isn’t quickly determined.

Design for Testability, often referred to as DFT, is a critical part of developing a new board. Here’s a link to a terrific class lecture from University of Maryland if you’re interested in seeing a well represented academic presentation of such an important topic.