As the boundary scan community continues looking for new ways to improve test procedures and achieve higher and higher fault coverage, we expect the test tools to compensate for shortcomings in silicon devices or board design. We are constantly exposed to new situations in boundary scan test and new approaches to using boundary scan to achieve better test fault coverage. One item standing in the way of higher, more accurate fault coverage is common tri-state control cells.
Common tri-state control cells are groups of pins on a common net. Just as the name suggests, they are tri-state pins, grouped together by a common function, sharing a boundary scan cell. Though this is efficient for circuitry, it poses some issues during JTAG test. For example, when a single pin on the common cell drives or senses a value, all the pins associated with that cell are forced to perform the same function, simultaneously. This is represented in the following drawing.
Un-handled common tri-state cells can have a negative impact on boundary scan test, dramatically reducing accuracy and fault coverage of opens and shorts tests because multiple pins sharing a common net drive in the same test vector, as displayed in the screen capture below.
In this image, you can see pins U23.AA14 and U36.AE30 are on net U23_AA14. This test is not accounting for the tri-state pins on the common control cell, ultimately compromising fault coverage.
This image shows the netlist view of the Mv6430 boundary scan device, while the following image displays the pins in an expanded view.