Many newcomers to JTAG test start their first projects knowing only that boundary scan testing is a requirement for new board design. The specifics of boundary scan, details of test strategy, or expected results are, for many, uncharted territory. In fact, most newcomers to boundary scan testing are uncertain as to what questions to ask or how to get started.
If you find that you are in a similar predicament, with a deadline for completing a boundary scan project looming ahead, help is just a phone call away. Flynn Systems is always available to discuss boundary scan in general, your project in particular, and how onTAP® can help you reach your goals. Flynn Systems offers a comprehensive suite of JTAG tools to meet your boundary scan testing needs, and we are always available to answer your questions, concerns, and inquiries regarding what JTAG is and how it can help you. But, first…
What Boundary Scan Does
The boundary scan test architecture provides a way to test interconnects between integrated circuits (ICs) on a board without using physical test probes. It contains cells within a device that can capture data from pin or core logic signals or force data onto pins. The captured data is shifted out and externally compared to other results. Forced test data is shifted into the boundary scan cells. This is all controlled from a data path called the scan path or scan chain.
By allowing direct access to nets, boundary scan can eliminate the need for a large number of test vectors. These test vectors are normally needed to properly initialize sequential logic. The benefits of boundary scan technology were quickly realized through shorter test times, higher test coverage, increased diagnostic capability and lower equipment cost.
A Brief History of JTAG Boundary Scan Testing
Boundary scan or the boundary scan test is also known as JTAG test or 1149.1. Joint Test Access Group (commonly referred to as JTAG) is a consortium of engineers from a multitude of electronics companies worldwide that formed over twenty years ago to meet the cries and pleas of standardization that the market was lacking. JTAG developed a standardized architecture for testing surface-mount devices applied to denser PCBs (Printed Circuit Boards), a test system commonly dubbed as JTAG or JTAG testing.
In the early 1980s, most PCB testing was achieved using the in-circuit bed-of-nails testers, which generally required physical access to all the devices on the board. This In-Circuit bed-of-nails technique provided an efficient and affordable method of testing boards. However, to meet the growing demands of miniaturization, denser (or layered) printed circuit boards began to dominate the market. This posed a huge problem for testing the electrical connectivity between devices, because board density and complex layering prevented the IC pins from being physically probed. Adding to this initial problem was the fact that real estate on boards was becoming a premium: the demand called for more devices with more information on smaller boards. Chip manufacturers met that demand with surface-mount technology.
As good as that was for shrinking technology, surface-mount packaging added complexity to the whole test process, not to mention board layout. Board design layout now had to provide test points for the bed-of-nails fixtures. Adding test points added noise to the board being tested, which created more complexity, more headaches, more delays and more financial cost. Without adding costly test points, access to IC pins could no longer be counted on and engineers as well as chip manufacturers had no set of standards by which to design, build and test. Enter the JTAG consortium.
The Joint Test Action Group originally began with participation from just European electronics companies in the mid-80s. As they sought to devise a specification for boundary scan testing, North American companies joined in the effort and the consortium gained sponsorship from the IEEE.
By 1990, that specification was ready to become the standard for boundary scan test. It was published as IEEE Std. 1149.1 and remains the foundation for boundary scan architecture. In 1994, an addition to the standard was made, which contained the Boundary Scan Description Language, more commonly known as BSDL. The BSDL IEEE supplement to 1149.1 describes the logic content of boundary scan compliant devices.
While the JTAG consortium remains active, adding more standards for boundary scan testing, the IEEE 1149.1 standard is the foundation upon which additional standards was built.
Flynn Systems Corporation, a boundary scan vendor, offers onTAP, a dynamic PC-based boundary scan test software suite. onTAP Boundary Scan provides a cost-effective test solution which encompasses the entire life cycle of a product from development through production. onTAP Boundary Scan technology offers solutions to handle problems such as:
- Boards that include components assembled on both sides, burying most of the through-holes, thus making them inaccessible
- Small-size products that do not have test points, making it difficult or impossible to probe suspected nodes
- Loss of physical access to fine pitch components, making it complicated to distinguish between manufacturing and design issues
For more information regarding onTAP or Boundary Scan, contact Flynn systems at
(603)-598-4444 or visit the website at www.flynn.com.