How to Purchase onTAP Boundary Scan Software
If board testing is taking up too much of your time,
we can help!…
With over 25 years of experience helping engineers and technicians solve their board test problems, Flynn Systems’ knows how critical board testing is.
We understand that you need a lab tool that lets you gain direct control of boundary scan pins on your board as well as the flexibility to drive and sense JTAG and TAP pins. It’s possible you may even need the capability to program FLASH, FPGAs, and CPLDs. Most importantly, you need this lab tool to be fast, accurate, and cost-effective. We developed circuit trace with you in mind.
Get ready to experience the power to easily trace, control, and measure the boundary scan pins on your printed circuit board with circuit trace.
Thank you for your interest in onTAP Series 4000. We are proud to offer this complete boundary scan/ JTAG solution at an attractive value– typically at least 20% less than our competitors.
Individual, custom quotes are easily obtained by contacting the Flynn Systems’ Sales Department. Feel free to call (603-598-4444 x 100) or email us at Sales@flynn.com and simply reference the part numbers in which you are interested. If you are uncertain about your requirements, don’t hesitate to give us a call.
Let Us Show You Around onTAP
Flynn Systems offers a free 30-day evaluation copy of onTAP. We will also supply evaluators with a loaner TAP CONNECT JTAG Controller to use on a live onTAP application throughout the evaluation period. The onTAP evaluation download is a fully functional version of the software, so you are not limited in your test development—you will be able to develop and run interconnect tests, program Flash, develop cluster tests, and using onTAP’s ProScan, you can get a good look at all those pins on large pin-count BGAs.
Our Tech Support team is always available to assist with your test set-up and to answer any questions you may have.
We look forward to working with you!
The Flynn Systems Development Team
onTAP Boundary Scan Software Products and Descriptions
The onTAP Boundary Scan / JTAG Test Development System includes all of the necessary JTAG software tools to develop and run comprehensive, reliable onTAP tests that deliver robust JTAG solutions.
All onTAP Software is IEEE 1149.1 & IEEE 1149.6 compliant. Each license is perpetual and considered a single-seat, single-user license. Portability for any onTAP License is an option and may be configured in any of the onTAP Licenses.
onTAP operates on Windows 7, 8 and 10. For larger applications, onTAP may require 100 MB RAM while running and files can exceed 1 GB hard drive space. Dongle-based Portable Licenses and the TAP CONNECT JTAG Controller require USB 2.0 ports.
Below, you will find the part number along with a brief description of each onTAP component.
Please note: Part numbers for International Quotes and Sales will show an –I suffix (e.g., FS-7002-I).
To receive a quote, please call us at 603-568-4444 or email us at Sales@flynn.com
onTAP License Types
|FS-7002||onTAP Development license includes Cluster Test, a Portability Option, One Year Technical Support. This is a perpetual License including: Automated Test Development Environment and Run-Time Test Environment, cluster test capability, ProScan Graphical Debugger with netlist browser, pin-level diagnostics (visual and reports), pin-wiggler, built-in netlist merge, over two dozen CAD netlist readers. Portability options: either USB dongle with embedded license, embedded license in a TAP CONNECT JTAG Controllers, or Network License Manager.
Cluster Test uses DTS Models to test circuit clusters, I2C, non-JTAG devices, such as memory devices, or to program FLASH devices; access to a library of other devices, such as DDR4, DDR3, SDRAM, is also available at no additional charge.
DLL capability is included in the Development License when DLL licenses are purchased in conjunction with the Development License. One Year Technical Support is included.
|FS-9402||onTAP DLL is typically used with third-party test executives, such as National Instruments’ LabView, TestStand, or custom test executives. The Dynamic Link Library runs all onTAP SVF test files and provides run-time control of tests and diagnostics. UI programs are available is C++ and C#.
When purchasing an onTAP DLL License with the onTAP Development License, Flynn Systems will provide an additional DLL License with the Development License Station at no extra charge. The addition of the DLL License with the Development License provides the opportunity to test and debug from one station before porting the tests to the DLL Test/Production environment. One Year Technical Support included.
|FS-9502||onTAP MTO includes Cluster Test, Portability Option, One Year Technical Support. The MTO is a perpetual License with the same UI as the Development license. It provides all test and diagnostic information as the full Development License, however, access to Development Screens is restricted so that developed tests may not be altered while in a Manufacturing/Test environment. Portability options: either USB dongle with embedded license, embedded license in a TAP CONNECT JTAG Controller, or Network License Manager (NLM).|
Flynn Systems offers three types of JTAG Controllers for use with onTAP software: the Standard Controller (1.8V – 5.5V), the Low Voltage Controller (.99V – 3.6V) and the new Low Voltage/Low Impedance Controller designed to support Intel’s Core i7 and Atom applications.
Only one piece of hardware is required to run onTAP: the Standard onTAP TAP CONNECT JTAG Controller, the Low Voltage JTAG Controller or the Low Impedance JTAG Controller. Software licenses may be embedded in each Controller type for portability. Multiple chain applications (more than two chains) require additional controllers.
All three TAP CONNECT JTAG Controllers accept two industry-standard connectors–Xilinx Fly Leads or Ribbon-Style Cable–as well as custom adapters.
|FS-9165||onTAP TAP CONNECT JTAG Controller: Designed exclusively for onTAP, the TAP CONNECT Controller offers dual-channel, adjustable TCK rate up to 30 MHz, used for Flash programming, JTAG test, including cluster testing of non-JTAG devices such as Memory devices; can also be used for FPGA, CPLD, PROM configuration programming, as well as general purpose PIO. The standard TAP CONNECT JTAG Controller operates over a voltage range of 1.8V – 5.5V, adjusting to an external voltage reference or using an internal voltage source.|
|FS-9162||onTAP TAP CONNECT JTAG Low Voltage Controller: offers all the features of the TAP CONNECT JTAG Controller, except the Low Voltage controller operates over a voltage range of 0.95V – 3.6V, adjusting to an external voltage reference or using an internal voltage source.|
|FS-9161||onTAP TAP CONNECT JTAG Low Voltage/Low Impedance Controller: Like the Low Voltage Controller, the TAP CONNECT JTAG Low Voltage/Low Impedance Controller offers the same features as the standard TAP Controller. In addition, the 1.05V TAP voltages, 50 Ohm pull-up and pull-down resistors and common TDI and TDO pin connections for multiple chains, all found in Intel’s Core i7 and Atom applications, are supported in the TAP CONNECT JTAG Low Impedance Controller.|
License Portability Options
|FS-7003||USB Security key/Dongle with license embedded in the dongle permits moving the license among multiple machines where the dongle is installed.|
|onTAP TAP CONNECT JTAG Controller with license embedded in the controller pod permits moving the license among multiple machines wherever the Controller is installed on the machine in use. All three controller types accept the embedded license.|
|FS-9055||onTAP Network License Manager: allows multiple client licenses to be placed on a central server and individually issued to multiple client computers.|
onTAP Features List
onTAP is compliant with IEEE Std. 1149.1 / 1149.6 and BSDL standards. The basic onTAP package includes, but is not limited to, the following features:
Test Development System that provides (FS-7002):
- Automatic Test Generation (ATG) of TAP integrity and interconnect tests based on board netlists and BSDL files
- Tests include TAP integrity, opens and shorts, pull-up/down resistors, bus-wire, and mid-state shorts
- BSDL syntax checking
- Industry-standard Serial Vector Format (SVF) file output, extended with flow-control inserts
- DTS, a C-like modeling language for memory/cluster tests and user-defined tests, automatically inserts flow control statements into SVF test files
- Cluster Test and FLASH Programming
- Transparency tools, including control of buffer/transceiver enable and direction pins
- Pin constraints and guards
- Test Palette selections to customize tests
- Testability information and Fault Scoring reports
- Netlist merging
Run-Time System with Scan Sequencer offers:
- Test Program Executive – select and run one or more scans
- Pin-level diagnostic messages
- ProScan display with breakpoints, single-stepping, and display of program variables
- In-System Programming
- Two test screens: one for debug and one for Manufacturing.
- Burn-in controls
- Multiple chain testing
- Runs standard SVF files and interprets embedded flow control instructions
View Application’s Signals:
- Browse through netlists to sample and view system level application signals at any circuit location based on JTAG SAMPLE instruction
Pin Wiggler enables user to:
- Set pin values at any output
- Observe, capture values at all scannable input pins on a selected net
Script and Command Files + User-Defined Tests allow user to:
- Incorporate private instructions to define customized scans
- Establish specific drive/sense conditions for selected pins
Debug Tools provide:
- Break-at-vector and single stepping
- Loop Switch
- Parse SVF to view Drive/Sense at each pin
Virtual Pins, Transparency and Bus Management automatically:
- Reaches “through” resistors and buffers
- Connects scannable and cluster pins
- Dynamically manages accessible direction and enable control pins
- Run-Time DLL
- USB Portable License Upgrade (dongle-based)
- Manufacturing Test Only Option
- onTAP TAP CONNECT JTAG Controller Standard Voltage
- onTAP TAP CONNECT JTAG Controller Low Voltage
- onTAP TAP CONNECT JTAG Controller Low Voltage/Low Impedance
The onTAP TAP CONNECT JTAG Controller
The onTAP TAP CONNECT JTAG Controller provides JTAG test and programming support for onTAP Boundary Scan Software. It offers higher speeds and simplified operation in both single and multiple-chain (multiple controllers) applications.
The Controller, either standard voltage, low voltage or low voltage-low impedance, may be used for the following applications:
- JTAG Test, including memory and cluster test
- Flash programming
- FPGA, CPLD and PROM configuration
- General purpose I/O
- The TAP CONNECT JTAG Controllers also provide the capability to run two chains at speeds up to 30MHz.
The TAP CONNECT JTAG Controller includes either two ribbon cable headers for direct connection to Xilinx-style headers or two flying lead connectors. Altera and other custom adaptors are available. The TAP CONNECT JTAG Controller attaches to a USB port on a PC with a Hi-Speed USB A-to-Mini cable.
The Cluster Test
Once an interconnect test has been developed, onTAP users frequently ask how to get started with cluster testing and flash programming. We have provided them with a way that is both efficient and flexible. Our cluster testing and flash programming models are reusable and may be adapted to other devices, as well as to application specific circumstances, such as demuxing a bus.
Memory and cluster testing is a powerful technique to check the connectivity between boundary scan pins and non-JTAG logic. Reusable test models for memory and other types of logic may be prepared in DTS, a high-level modeling language. DTS brings C-like flow control and expressions to the development of test models for non-JTAG devices.
Models may be prepared without regard to the details of boundary scan implementation, since onTAP’s Virtual Nails serializes a model’s test vectors into scans and automatically associates boundary scan pins, to act as driver/sensors, with non-JTAG device pins.
A simple example shows how DTS models can be used to set and test pin values on non-JTAG logic follows.
Sample DTS Model
The example below will write some data into memory addresses and call a clock. Data will then be read back from those addresses.
Mid-state shorts are bridging faults that result in a mid-state voltage level rather than a hard low or high level. In our experience at Flynn Systems when working with customers, we have found the condition occurs where short circuits exist as follows:
- between some boundary-scan pins on FPGA devices when only one boundary scan pin exists on a PCB net.
- across pins of resistor networks where the resistors lie between the shorts fault and scannable pins, and again where single boundary scan pins exist on the nets.
Mid-state shorts, like any bridging fault, can result in system level applications failures if not detected and cleared. The difficulty is that these shorts will not be detected by traditional boundary scan shorts detection algorithms that depend on sensing zero or one logic levels. The reason is that at the capture cell on single-pin nets, the capture value is equal to the value being actively driven from the same pin.
In the case of the resistor network, it is easy to see how the resistors can isolate the capture value from the value measured at the physical short. In the case of the FPGA pins the reasons are not quite so clear, but apparently sufficient impedance exists between the bidirectional cells and physical pins so that the input cell sees the value driven from the drive cell, not the value measured at the physical short.
Seen at P1 1110001111000011110000 // R1 isolates P1 from shorts value Z
Seen at P2 1110000000111111111000 // R2 isolates P2 from shorts value Z
Seen at Short 111000ZZZZZZZ1111Z000 // Z value results at opposing values
How Can MID-STATE Shorts be Detected?
As might be expected, MID-STATE shorts can be detected by a test pattern that uses tri-state, high impedance values, Z, in combination with zero and one values. One difficulty however, is that since Z is a passive condition and this approach is likely to result in unpredictable numbers of false failures. Another problem is that the number of potential test scans can be quite large.
onTAP addresses these difficulties in several ways. First, to achieve a manageable number of test patterns, standard Wagner test patterns, popular in boundary scan testing and known for their compactness and effectiveness, are employed. But instead of just using only 0-1 test patterns, 0-Z and 1-Z patterns are also used. This is effective and will detect the shorts, but will inevitably also produce false failures.
To deal with the false failures, onTAP actively interrogates all indicated net combinations at run time with a more exhaustive 0-1-Z pattern that eliminates false failures, but indicates any MID-STATE shorts conditions.
TestGen and AC Testing
AC Testing, also referred to as Dot 6 (from the IEEE Std. 1149.6) or AC EXTEST, provides a method to handle testing of the newer digital devices, such as the popular Broadcom communication devices. Incorporating the AC Testing into onTAP’s test tools expands users’ test capabilities, flexibility, and further enhances test fault coverage in a number of ways. Most apparent is the productivity gain achieved by testing to both IEEE 1149.1 and IEEE 1149.6 standards. The IEEE 1149.6 feature enables users to test AC Coupled circuits and differential pairs to the industry standard protocol. Adding these two elements to a test not only increases test fault coverage, but also creates a more robust and reliable test by incorporating additional aspects of the board in the test.
onTAP’s TestGen screen provides almost unlimited capability to shape and customize test plans, in addition to providing traditional pre-set test generation. Modern applications such as the popular Broadcom communication devices that support IEEE 1149.6 AC testing, often require insertion of custom initialization scans which TestGen now accomplishes in a direct manner, as the image below demonstrates.
Inserting an External File into the Test Plan:
External text files containing SVF or DTS cluster instructions can be inserted into a TestPlan. They will appear in the compiled SVF at the position that they are dropped in the TestPlan. The procedure is:
- Drag and drop, External File Name or SVF, into a position on the TestPlan.
- Click on the inserted instruction and then add a filename in the Options Edit box. The filename must be enclosed in quotes.
onTAP® Boundary Scan Requirements
In order to develop a project with onTAP Software, you will need the following:
BSDL Files for the devices to be tested
(BSDL = Boundary Scan Description Language) Most BSDL files can be found on the Manufacturer’s web site. Should you encounter difficulty obtaining a file, feel free to contact us at firstname.lastname@example.org. We would be happy to look through our archives.
Board Level Netlist files
A netlist file is the PCB’s roadmap and it is a very important piece of information for onTAP. The netlist file tells onTAP what the device types are, the circuit locations and their pin-to-pin connections. onTAP uses the BSDL files and your board netlist file to automatically create boundary scan tests. This includes infrastructure tests, interconnect tests and memory/cluster tests. Most often, the netlist file will accompany the PCB. In instances where the netlist file does not accompany the board, you should contact the board designer and ask for the netlist file in one of the many CAD formats that onTAP accepts. To view a listing of accepted CAD netlist formats, please follow this link: http://www.flynn.com/ontap-supported-netlist-readers-2
Evaluating a Boundary Scan Project
When you have the required information (BSDL files and Board Netlist Files) and if you would like assistance from us, you may send that information to email@example.com . We will review your application and consult with you as to what configuration of onTAP you will need.
Included in the price of each base product is one year of support. Support covers the license, unlimited access to updates and upgrades, plus hardware purchases. In addition, one-on-one tech support is available to provide answers to questions about onTAP’s use, functionality, and performance. Although your onTAP license never times out, after one year, a new support contract is required in order to continue coverage on the support, hardware and all updates and upgrades.
Delivery of Product
All software deliveries are electronically transmitted, 24 hours ARO. All hardware components and where company policy requires a physical shipment of the software, said shipment shall be made generally one day ARO. Shipping and handling charges are not included in the price of the software and/or hardware.