Basic Boundary Scan Building Blocks
The Joint Test Action Group (JTAG), an association of electronic industries involved in the design and testing of printed circuit boards after their manufacture, developed a method used to verify board designs and test printed circuit boards.
The work of JTAG was later developed by the Institute of Electrical and Electronics Engineers (IEEE) into what is now referred to as IEEE Standard 1149.1-1990, Standard Test Access Port and Boundary-Scan Architecture, now known as Boundary Scan or JTAG Test.
Boundary scan provides a means for testing connections on printed circuit boards or sub-blocks inside an integrated circuit. Boundary scan is also widely used as a debugging method to watch integrated circuit pin states, measure voltage, or analyze sub-blocks inside an integrated circuit.
The major advantage of Boundary Scan is the ability to set and read the values on pins without direct physical access.
To accomplish this testing, the addition of at least one test cell which is connected to each pin of the device and which can selectively override the functionality of that pin is required. Each test cell may be programmed via the JTAG scan chain to drive a signal onto a pin and thus across an individual trace on the board; the cell at the destination of the board trace can then be read, verifying that the board trace properly connects the two pins. If the trace is shorted to another signal or if the trace is open, the correct signal value does not show up at the destination pin, indicating a fault.
Figure 1: This diagram depicts a boundary scan cell at a pin location inside an integrated circuit that can be used for testing interconnects.
How does it work?
IEEE STD 1149.1 is defined in the top level schematic of the test logic which is made up of three principal blocks: The TAP (Test Access Port) Controller, the Instruction Register (IR), and the Data Register (DR).
TAP Controller – The TAP Controller is a state machine whose transitions are controlled by the TMS (Test Mode Select) signal which reacts to the control sequences provided through the TAP, generating clock and control signals needed for proper operation of the other circuit blocks.
Instruction Register (IR) -The Instruction Register is a shift register-based circuit which is serially loaded with the instruction that is to be carried out.
Data Register (DR) -Data Registers are a bank of shift register-based circuits. The impetus needed by an operation is serial loaded into the data resisters which are selected by the current instruction. After the operation is executed, the results can be transferred out for examination.
The Test Access Port (TAP)
The Test Access Port (Figure 2) is the JTAG interface which contains four pins which drive the circuit blocks and control which operations have been specified. The TAP provides for the serial loading and unloading of both instructions and data via the pins of the TAP. The four pins of the Test Access Port include:
TCK (Test Clock) Sequences the TAP controller along with all of the JTAG registers
TMS (Test Mode Select) Provides the Test Mode Signal to the TAP Controller. The state of TMS at the rising state of TCK determines the sequence of states for the TAP controller. TMS has an internal pull-up resistor on it to provide a logic 1 to the system if the pin is not driven.
TDI (Test Data In) is the serial data input to all JTAG instruction and data registers. The state of the TAP controller as well as the particular instruction held in the instruction register determines which register is fed by TDI for a specific operation. TDI is sampled into the JTAG registers on the rising edge of TCK.
TDO (Test Data Out) is the serial data output for all JTAG instruction and data registers. The state of the TAP controller as well as the particular instruction held in the instruction register determines which register feeds TDO for a specific operation. Only one register (instruction or data) is allowed to be the active connection between TDI and TDO for any given operation. TDO changes state on the falling edge of TCK and is only active during the shifting of data through the device. This pin is tri-stated at all other times.
TRST (Test Reset) is an optional pin which can reset the TAP controller’s state machine, when it is available.
Figure 2: The TAP’s four mandatory pins, TCK, TDI. TDO, TMS plus an optional TRST reset pin, provide boundary scan test access.
The TAP Controller
The JTAG TAP Controller is a 16-state finite state machine (Figure 3), which controls the scanning of data into the various registers of the JTAG architecture. The state of the TMS pin at the rising edge of TCK is responsible for determining the sequence of state transitions. There are two state transition paths for scanning the signal at TDI into the device, one for shifting in an instruction to the instruction register and one for shifting data into the active data register as determined by the current instruction.
The TAP Controller States
Test-Logic-Reset is entered on power-up of the device and whenever at least five clocks of TCK occur with TMS held high. Entry into this state resets all JTAG logic to a state such that it does not interfere with the normal component logic, and causes the IDCODE instruction to be forced into the instruction register.
Run-Test-Idle enables certain operations to occur depending on the current instruction. For IEEE STD 1532 compliant devices, this state causes generation of the program, verify and erase pulses when the associated in-system programming (ISP) instruction is active.
Select-DR-Scan is a temporary state entered prior to performing a scan operation on a data register or in passing to the Select-IR-Scan state.
Select-IR-Scan is a temporary state entered prior to performing a scan operation on the instruction register or in returning to the Test-Logic-Reset state.
Capture-DR enables data to be loaded from parallel inputs into the data register selected by the current instruction on the rising edge of TCK. If the selected data register does not have parallel inputs, the register retains its state.
Shift-DR shifts the data, in the currently selected register, towards TDO by one stage on each rising edge of TCK after entering this state.
Exit1-DR This is a temporary state that enables the option of passing on to the Pause-DR state or transitioning directly to the Update-DR state.
Pause-DR This is a wait state that enables shifting of data to be temporarily halted.
Exit2-DR This is a temporary state that enables the option of passing on to the Update-DR state or returning to the Shift-DR state to continue shifting in data.
Update-DR causes the data contained in the currently selected data register to be loaded into a latched parallel output (for registers that have such a latch) on the falling edge of TCK after entering this state. The parallel latch prevents changes at the parallel output of these registers from occurring during the shifting process.
Capture-IR enables data to be loaded from parallel inputs into the instruction register on the rising edge of TCK. The least two significant bits of the parallel inputs must have the value 01 as defined by IEEE Std. 1149.1, and the remaining bits, if any, are free to be used for any purpose. Most Xilinx devices use these bits to indicate security and internal control logic status.
Shift-IR shifts the values in the instruction register towards TDO by one stage on each rising edge of TCK after entering this state.
Exit1-IR is a temporary state that enables the option of passing on to the Pause-IR state or transitioning directly to the Update-IR state.
Pause-IR is a wait state that enables shifting of the instruction to be temporarily halted.
Exit2-IR is a temporary state that enables the option of passing on to the Update-IR state or returning to the Shift-IR state to continue shifting in data.
Update-IR causes the values contained in the instruction register to be loaded into a latched parallel output on the falling edge of TCK after entering this state. The parallel latch prevents changes at the parallel output of the instruction register from occurring during the shifting process.
Figure 3 – TAP State machine: All states have two exits, so all transitions can be controlled by the single TMS signal sampled on TCK. The two main paths allow for setting or retrieving information from either a data register or the instruction register of the device. The data register operated on (e.g. BSR, IDCODES, BYPASS) depends on the value loaded into the instruction register.
Mandatory Boundary Scan Instructions
BYPASS–the BYPASS instruction enables rapid movement of data to and from other components on a board that are required to perform test operations.
SAMPLE/PRELOAD—the SAMPLE/PRELOAD instruction enables a snapshot of the normal operation of a component to be taken and examined. It enables data values to be loaded onto the latched parallel outputs of the Boundary-Scan shift register prior to the selection of other Boundary-Scan test instructions.
EXTEST. The EXTEST instruction enables testing of off-chip circuitry and board level interconnections.
Optional Boundary Scan Instructions
INTEST. The INTEST instruction enables testing of the on-chip system logic while the components are already on the board.
HIGHZ. The HIGHZ instruction forces all drivers into high impedance states.
IDCODE. The IDCODE instruction enables blind interrogation of the components assembled onto a printed circuit board to determine what components exist in a product.
USERCODE. The USERCODE instruction enables a user-programmable 32 bit identification code to be shifted out for examination. This can be used to identify the programmed function of the component.
JTAG testing systems like Flynn System’s onTAP allow the import of design ‘netlists’ from CAD/EDA systems combined with the BSDL models of boundary scan/JTAG compliant devices to automatically generate test applications. Common types of test include:
- Scan-path ‘infrastructure’ or integrity
- Boundary-scan device pin to boundary-scan device pin ‘interconnect’
- Boundary-scan pin to memory device or device cluster (SRAM, DRAM, DDR etc.)
- Arbitrary logic cluster testing
When used during manufacturing, such systems also support non-test but affiliated applications such as in-system programming of various types of flash memory: NOR, NAND, and serial (I2C or SPI).
Boundary scan supports the following board-level test functions:
- Testing of the interconnect wiring on a printed circuit board for shorts, opens, and bridging faults
- Testing of clusters of non-boundary-scan logic
- Identification of missing, incorrectly oriented, or incorrectly selected components
- Identification of fixture problems
- Limited testing of individual chips on a board