Posted on June 12, 2017 in JTAG, JTAG Boundary Scan, onTAP, onTAP JTAG Blog

Once a board developer passes along the new board and all related files and procedures to a test developer, the boundary scan test process can begin. We recommend including the TAP Integrity Test at the beginning of your interconnect test because the TAP contains pins associated with the test access controller, e g., the TAP […]

Chip manufacturers are now producing multichip modules (MCMs) that may include two or more arrays of devices within a single package. These modules can be tested using JTAG test pattern generation of the devices while on a PCB. To incorporate JTAG testing of MCMs there are several things that are needed: a netlist of the […]

If a chain of devices consisted only of boundary scan (JTAG) compliant devices, there would not be too much required testing. However, today’s boards contain complex, non-JTAG devices that interact with the boundary scan devices. Testing just the JTAG devices on the board is always an option. However, developing a test that takes into account […]

Posted on February 10, 2017 in Boundary Scan, Boundary Scan Test, onTAP JTAG Blog

Not every boundary scan application experiences delays. Some run without any problems, but when there is a delay, oftentimes it can be traced back to lack of information from the board’s developer to the board’s tester.

Posted on May 11, 2016 in Boundary Scan Test, onTAP JTAG Blog

Introduction As miniaturization of PCBs became more desirable, denser (or layered) printed circuit boards began to dominate the market. Testing electrical connectivity between devices posed a huge problem because  board density and complex layering prevented the IC pins from being physically probed. The Joint Test Action Group (JTAG) developed a solution: boundary scan. The Joint Test […]